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keyboard4_4-and-seg7
- 4*4键盘扫描程序，并将键值利用七段数码管显示出来。芯片为Altera Cyclone EP1C6Q240C8。-It s very simple,for rookies.
usb_test
- altera cyclone 2c35开发板，测试usb通用串行总线,verilog编写的-altera cyclone 2c35 development board test usb Universal Serial Bus, verilog prepared
my_test_rw_pack9
- 基于Verilog HDL的SDRAM控制器。 实验条件： 工具：Quartus II 6.0 ,SignalTap II FPGA：Altera Cyclone EP1C12Q240C8N SDRAM：HY57V283220T-6-SDRAM controller based on Verilog HDL. Experimental conditions: Tools: Quartus II 6.0, SignalTap II FPGA: Altera Cyclon
EP3C10_Verilog
- ALTERA Cyclone ΙΙΙ EP3C10 开发板测试代码-ALTERA Cyclone ΙΙΙ EP3C10 development board test code
FA161-SCH
- 联华众科FPGA开发板FA161核心器件为 Altera Cyclone系列FPGA EP1C6，FA161板载有SDRAM，SRAM，FLASH方便制作各种应用，开发板所带资料中包括了上位机与开发板USB通信，上位机与开发板以太网通信，上位机与开发板串口通信例程。FA161板载有USB 1.1，USB 2.0(CY7C68013A)接口，以太网接口(RTL8019AS)。FA161上可以进行HDL程序开发，可以进行nios ii程序开发，可以结合MATLAB制作DSP Builder应用。FA
DE2_TVdecoder
- 基于altera cyclone ii的TV译码例程-demonstrations about TV decoder based on altera cyclone ii
yinpinxinhaofenxiyi1233412
- 基于Altera Cyclone II 系列FPGA嵌入高性能的嵌入式IP核(Nios)处理器软核的基于FFT的音频信号分析仪-Based on Altera Cyclone II series FPGA embedded high-performance embedded IP core (Nios) soft core processor FFT-based audio signal analyzer
xinhaoyuan
- DDS产生多种波形信号发生器，包括正弦波，三角波，方波，锯齿波。运行于Altera Cyclone FPGA平台。-DDS signal generator generates a variety of waveforms including sine, triangle wave, square wave, sawtooth wave. Running on Altera Cyclone FPGA platform.
2fsk_0516
- 运行于Altera Cyclone FPGA平台,基于DDS原理的FSK信号发生器，可产生FSK信号-Running on Altera Cyclone FPGA platform, based on the principle of DDS FSK signal generator for FSK signal
MOTO3--bujin
- 运行于Altera Cyclone FPGA平台,顶层为原理图方式，模块由VHDL编写的步进电机驱动程序。-Running on Altera Cyclone FPGA platform, the top of the schematic way, module consists of VHDL stepper motor driver.
MOTO3--zhiliu
- 运行于Altera Cyclone FPGA平台,顶层为原理图方式，模块由VHDL编写的直流电机驱动程序。-Running on Altera Cyclone FPGA platform, the top of the schematic way, the module VHDL prepared by the DC motor driver.
cmi
- 运行于Altera Cyclone FPGA平台,由VHDL编写的NRZ到CMI编码和CMI到NRZ解码程序。-Running on Altera Cyclone FPGA platform, VHDL prepared NRZ to CMI CMI to NRZ encoding and decoding procedures.
Manchester
- 运行于Altera Cyclone FPGA平台,由VHDL编写的NRZ到曼彻斯特编码和曼彻斯特编码到NRZ解码程序。-Running on Altera Cyclone FPGA platform, consisting in VHDL coding NRZ to Manchester and Manchester encoding to NRZ decoding process.
SDRAM_CONTROL_DE2
- 基于Altera公司的Cyclone II 2C35芯片和SDRAM芯片IS42S16400的sdram控制器（教学用）-Based on Altera Cyclone II 2C35 chips and SDRAM chips IS42S16400. the code realize a the sdram controller (for teaching)
am
- 利用altera的cyclone FPGA芯片，实现AM调制，并使用自带的逻辑分析仪仿真成功。-The use altera cyclone FPGA chip, AM modulation, and use its own logic analyzer successful simulation
dds
- 利用altera的cyclone FPGA芯片，模拟DDS原理，产生频率可调的正弦波，并使用自带的逻辑分析仪仿真成功-The use altera cyclone FPGA chip, analog DDS principle, have adjustable frequency sine wave, and use the built-in logic analyzer simulation success
fm
- 利用altera的cyclone FPGA芯片，实现FM调制，并使用自带的逻辑分析仪仿真成功-The use altera cyclone FPGA chip, FM modulation, and use its own logic analyzer successful simulation
uCOS-II-Cyclone-V-SoC
- 应用在ALTERA FPGA芯片的UCOS开发板实现代码,从micrium官网下载-μC/OS-II Example for the Cyclone V SoC Development Kit
ASS2_bench
- Verilog HDL for IRDA transmitter by DE2 board using Altera Cyclone II Quartus-Verilog HDL for IRDA transmitter by DE2 board using Altera Cyclone II QuartusII
SPI-Core_nguyen
- SPI Master Core HDL: VHDL 93 Compatibility: all FPGAs, CPLDs parameterization: - variable data width - Phase/polarity configurable - selectable buffer depth - serial clock devision due to system clock package usage: IEEE